This invention relates generally to interface circuits and, more particularly, to a circuit for interfacing transistor to transistor logic (TTL) circuits to complementary metal oxide semiconductor (CMOS) insulated gate field effect transistor circuits.
A number of circuits have been devised to address the problem of interfacing TTL circuits, which have logic voltage varations of 0.8 volts to 2.0 volts, to CMOS circuits which are designed for voltage swings of from 0 volts to 5 volts or higher. One class of circuits uses an inverter stage at the input of the interface circuit, with the inverters formed of appropriately sized and ratioed CMOS devices. These circuits are generally slow and must drive high capacitive loads. One method of increasing the speed of such circuits is described in U.S. Pat. No. 3,900,746 to Kraft et al. This method involves the use of a divertable current sink in the form of a third field effect transistor connected in series with the inverter. Although this is an improvement over prior art circuits, the series connection of the current sink with the N channel device on the output provides a resistance which limits the response time of the circuit.
Another drawback fo interface circuits of the inverter type is that the switching point of the circuit is very dependant upon the device threshold voltages. For devices with high thresholds operating at low temperatures, the input specifications are very difficult to maintain. Device thresholds are dependant upon manufacturing tolerances and may vary considerably. One approach to stabilizing the variations in operating point of an interface circuit is shown in U.S. Pat. No. 4,280,710 to Cohen et al., which is assigned to Harris Corporation. The circuit in Cohen is an interface circuit having a CMOS inverter with its N channel device being part of a controlled leg of a first current mirror and its P channel device being part of a controlled leg of a second current mirror. The other part of the controlled leg of the first current mirror is connected in series with the N channel device and in parallel with the P channel device and operates as a variable current source responsive to the input signal. The other part of the controlled leg of the second current mirror is likewise connected in series with the P channel device and in parallel with the N channel device and operates as a variable current sink responsive to the input signal. The controlling legs of the first and second current mirrors are connected to a reference voltage input. The components of the circuit are designed such that the operating point of the inverter is defined by the voltage on the reference voltage input. This approach stabilizes the switching point of the circuit and improves response time. However, considerable amounts of both power and area are consumed in the implementation of the circuit.
A third approach to the interfacing problem is illustrated by a class of circuits which employ classical differential input stages to stabilize the switching point. The differential stages are relatively slow, due to their linear voltage gain, and are also critically dependant on the stability of the reference voltage. Although the operating speed of the circuits can be increased, this is usually achieved at the expense of a considerable increase in power consumption.
An object of the present invention is to provide a TTL to CMOS interface circuit having a stabilized switching point and a fast response time.
Another object of the present invention is to provide a TTL to CMOS interface circuit which is relatively insensitive to reference voltage variations.
A further object of the present invention is to provide a TTL to CMOS interface circuit which is insensitive to variations in device tolerances over a wide range of operating and process conditions.
Still another object of the present invention is to provide a TTL to CMOS interface circuit which achieves the above objects without considerable increases in power consumption.
These and other objects of the invention are attained by an interface circuit having an input stage which includes a differential transistor pair and a current mirror to provide CMOS output voltage levels at an output terminal in response to TTL voltage levels at one of the inputs to the differential pair. The second differential pair input is connected to a reference voltage. To increase the response time of the circuit to a negative going input pulse, a first switching device, responsive to the voltage input, is connected from a first power supply terminal to the controlling leg of the current mirror. When the input voltage decreases, relative to the reference voltage, the switching device increases the current flow in the controllable leg of the current mirror. This increase is mirrored into the controlled leg of the current mirror which is connected to the output terminal. The increase in current flowing to the output terminal results in faster charging of the capacitance associated with the output terminal, decreasing the response time of the circuit. A second switching device, also responsive to the voltage at the circuit input, is preferably connected to the output terminal and to a second power supply terminal. When the voltage at the input increases relative to the reference voltage, the second switching device is activated to pull the output terminal low with minimal delay. The output terminal of the input stage may be buffered by one or more inverter circuits to provide both inverting and noninverting buffered outputs.
This circuit combines the precise switching of a linear differential input with the speed of a digital inverter to achieve the desired interfacing. The circuit requires low bias currents, is insensitive to process variations, and works over a wide range of reference voltages.
Other objects, advantages, and novel features of the interface circuit of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.